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INTEGRATED CIRCUITS
DATA SHEET
TDA9875 Digital TV Sound Processor (DTVSP)
Preliminary specification Supersedes data of 1997 Mar 20 File under Integrated Circuits, IC02 1998 Feb 13
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
CONTENTS 1 1.1 1.2 1.3 2 2.1 3 4 5 6 6.1 6.2 6.3 7 8 9 10 10.1 10.2 10.3 10.4 10.5 11 12 13 14 14.1 14.2 14.3 15 16 17 FEATURES Demodulator and decoder section DSP section Analog audio section GENERAL DESCRIPTION Supported standards ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section Description of the DSP Description of the analog audio section LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS I2C-BUS CONTROL Introduction Power-up state Slave receiver mode Slave transmitter mode Expert mode I2S-BUS DESCRIPTION EXTERNAL COMPONENTS PACKAGE OUTLINE SOLDERING Introduction Soldering by dipping or by wave Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
TDA9875
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
1 1.1 FEATURES Demodulator and decoder section
TDA9875
* Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF sources * SIF AGC with 21 dB control range * SIF 8-bit Analog-to-Digital Converter (ADC) * DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation * NICAM decoding (B/G, I and L standard) * Two-carrier multistandard FM demodulation (B/G, D/K and M standard) * Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound * Optional AM demodulation for system L, simultaneously with NICAM * Programmable identification (B/G, D/K and M standard) and different identification times. 1.2 DSP section 2.1 Supported standards The multistandard/multi-stereo capability of the TDA9875 is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted. M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. The AM sound of L/L' standard is normally demodulated in the 1st sound IF. The resulting AF signal has to be entered into the mono audio input of the TDA9875. A second possibility is to use the internal AM demodulator stage, however this gives limited performance. Korea has a stereo sound system similar to Europe and is supported by the TDA9875. Differences include deviation, modulation contents and identification. It is based on M standard. An overview of the supported standards and sound systems and their key parameters is given in Table 1. * Standby mode with functionality for SCART copies * Dual audio digital-to-analog converter from DSP to analog crossbar switch, bandwidth 15 kHz * Dual audio ADC from analog inputs to DSP * Two dual audio Digital-to-Analog Converters (DACs) for loudspeaker (Main) and headphone (Auxiliary) outputs; also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension. 2 GENERAL DESCRIPTION
The TDA9875 is a single-chip Digital TV Sound Processor (DTVSP) for analog and digital multi-channel sound systems in TV sets and satellite receivers.
* Digital crossbar switch for all digital signal sources and destinations * Control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft-mute * Plop-free volume control * Automatic Volume Level (AVL) control * Adaptive de-emphasis for satellite * Programmable beeper * Monitor selection for FM/AM DC values and signals, with peak detection option * I2S-bus interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and mute. 1.3 Analog audio section
* Analog crossbar switch with inputs for mono and stereo (also applicable as SCART 3 input), SCART 1 input/output, SCART 2 input/output and line output * User defined full-level/-3 dB scaling for SCART outputs * Output selection of mono, stereo, dual A/B, dual A or dual B * 20 kHz bandwidth for SCART-to-SCART copies
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
2.1.1 Table 1 ANALOG 2-CARRIER SYSTEMS Frequency modulation SOUND SYSTEM mono A2+ A2 mono A2 A2* CARRIER FREQUENCY (MHz) 4.5 4.5/4.724 5.5/5.742 6.0 6.5/6.742 6.5/6.26 FM DEVIATION (kHz) NOM./MAX./OVER 15/25/50 15/25/50 27/50/80 27/50/80 27/50/80 27/50/80
1 1 1 1
TDA9875
MODULATION SC1 mono
2(L 1
STANDARD M M B/G I D/K D/K Table 2
SC2 -
2(L
BANDWIDTH/ DE-EMPHASIS (kHz/s) 15/75 15/75 (Korea) 15/50 15/50 15/50 15/50
+ R)
- R)
2(L + R)
R - R R
mono
2(L
+ R)
2(L + R)
Identification for A2 systems PARAMETER A2/A2* 54.6875 kHz = 3.5 x line frequency pilot frequency 117.5 Hz = -------------------------------------133 pilot frequency 274.1 Hz = -------------------------------------57 50% A2+ (KOREA) 55.0699 kHz = 3.5 x line frequency pilot frequency 149.9 Hz = -------------------------------------105 pilot frequency 276.0 Hz = -------------------------------------57 50%
Pilot frequency Stereo identification frequency Dual identification frequency AM modulation depth 2.1.2 Table 3
2-CARRIER SYSTEMS WITH NICAM NICAM SC1
STANDARD FREQUENCY TYPE (MHz) B/G I D/K L Note 5.5 6.0 6.5 6.5 FM FM FM AM
SC2 ROLL-OFF NICAM (MHz) DE-EMPHASIS (%) CODING DEVIATION NICAM INDEX (%) (kHz) NOM/MAX. NOM./MAX. - - - 54/100 27/50 27/50 27/50 - 5.85 6.552 5.85 5.85 J17 J17 J17 J17 40 100 40 40 note 1 note 1 not yet defined note 1
MODULATION
1. See "EBU specification" or equivalent specification.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
2.1.3 SATELLITE SYSTEMS
TDA9875
An important specification for satellite TV reception is the "Astra specification". The TDA9875 is suited for the reception of Astra and other satellite signals. Table 4 FM satellite sound CARRIER FREQUENCY (MHz) 6.50(1) 7.02/7.20 7.38/7.56 7.74/7.92 8.10/8.28 MODULATION INDEX 0.26 0.15 0.15 0.15 0.15 MAXIMUM FM DEVIATION (kHz) 85 50 50 50 50 MODULATION mono m/st/d(2) m/st/d(2) m/st/d(2) m/st/d(2) BANDWIDTH/ DE-EMPHASIS (kHz/s) 15/50(1) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3)
CARRIER TYPE Main Sub Sub Sub Sub Notes
1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis of 60 s, or in accordance with J17, is available. 2. m/st/d = mono or stereo or dual language sound. 3. Adaptive de-emphasis = compatible to transmitter specification. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9875 SDIP64 DESCRIPTION plastic shrink dual in-line package; 64 leads (750 mil) VERSION SOT274-1
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
4 BLOCK DIAGRAM
SIF2 10 P1 P2 ADDR1 ADDR2 SCL SDA 9 20 3 13 4 5 I2C-BUS INTERFACE INPUT SWITCH AGC, ADC SUPPLY SOUND IF (SIF) 7 6 11 8 VDDA1 VSSA1 Vref1 Iref SIF1 12
TDA9875
handbook, full pagewidth
IDENTIFICATION
FM (AM) DEMODULATION
NICAM DEMODULATION
TIMING DETECTION DAC
19 2 1
Vtune NICAM PCLK
33 XTALI XTALO SYSCLK 18 17 21 CLOCK DEMATRIX NICAM DECODER 34 36 37 31 32 ANALOG CROSSBAR SWITCH 29 47 48 PEAK DETECTION LEVEL ADJUST LEVEL ADJUST 51 52 63 62
SCIR1 SCIL1 SCIR2 SCIL2 EXTIR EXTIL MONOIN SCOR1 SCOL1 SCOR2 SCOL2 LOR LOL
SDI1 SDI2 SDO1 SDO2 SCK WS
27 26 25 24 22 23 DIGITAL SELECT 15 64 14 49 16 DIGITAL SUPPLY DAC(2) I2C-BUS AUDIO INTERFACE 42 41 ADC(2) 45 44 CAPL2 CAPL1 CAPR1 CAPR2
VDDD1 VDDD2 VSSD1 VSSD2 CRESET
54 55 38 43 35
PCAPR PCAPL VDDA2 VSSA2 VSSG Vref2 Vref(p) Vref(n) VDDA3 VSSA3 Vref3
TDA9875
AUDIO PROCESSING
SUPPLY DAC
46 39 40
TEST1 TEST2
28 30 TEST DAC(2) DAC(2) SUPPLY DAC
59 56 53
REFERENCE
SUPPLY OPERATIONAL AMPLIFIERS 61 MOL 60 MOR 58 AUXOL 57
50
VSSA4
MGK107
AUXOR
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
5 PINNING SYMBOL PCLK NICAM ADDR1 SCL SDA VSSA1 VDDA1 Iref P1 SIF2 Vref1 SIF1 ADDR2 VSSD1 VDDD1 CRESET XTALO XTALI Vtune P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 MONOIN TEST2 EXTIR EXTIL SCIR1 SCIL1 VSSG SCIR2 SCIL2 VDDA2 Vref(p) Vref(n) 1998 Feb 13 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O O O I I I/O supply supply - I/O I - I I supply supply - O I O I/O O I/O I/O O O I I I I I I I I I - I I supply - - NICAM clock output at 728 kHz serial NICAM data output at 728 kHz first I2C-bus slave address modifier I2C-bus clock I2C-bus data supply ground 1; analog front-end circuitry analog supply voltage 1; analog front-end circuitry resistor for reference current generator; analog front-end circuitry first general purpose I/O pin sound IF input 2 reference voltage; analog front-end circuitry sound IF input 1 second I2C-bus slave address modifier supply ground 1; digital circuitry digital supply voltage 1; digital circuitry capacitor for power-on reset crystal oscillator output crystal oscillator input tuning voltage output for crystal oscillator second general purpose I/O pin system clock output I2S-bus clock I2S-bus word select I2S-bus data output 2 I2S-bus data output 1 I2S-bus data input 2 I2S-bus data input 1 first test pin; connected to VSSD1 for normal operation audio mono input second test pin; connected to VSSD1 for normal operation external audio input right channel external audio input left channel SCART 1 input right channel SCART 1 input left channel ground guards; audio analog-to-digital converter circuitry SCART 2 input right channel SCART 2 input left channel analog supply voltage 2; audio analog-to-digital converter circuitry DESCRIPTION
TDA9875
positive reference voltage; audio analog-to-digital converter circuitry reference voltage ground; audio analog-to-digital converter circuitry 7
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
SYMBOL CAPL1 CAPL2 VSSA2 CAPR2 CAPR1 Vref2 SCOR1 SCOL1 VSSD2 VSSA4 SCOR2 SCOL2 Vref3 PCAPR PCAPL VSSA3 AUXOR AUXOL VDDA3 MOR MOL LOL LOR VDDD2
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
I/O - - supply - - - O O supply supply O O - - - supply O O supply O O O O supply
DESCRIPTION filter capacitor pin 1; audio analog-to-digital converter, left channel filter capacitor pin 2; audio analog-to-digital converter, left channel supply ground 2; audio analog-to-digital converter circuitry filter capacitor pin 2; audio analog-to-digital converter, right channel filter capacitor pin 1; audio analog-to-digital converter, right channel reference voltage; audio analog-to-digital converter circuitry SCART 1 output right channel SCART 1 output left channel supply ground 2; digital circuitry supply ground 4; audio operational amplifier circuitry SCART 2 output right channel SCART 2 output left channel reference voltage; audio digital-to-analog converter and operational amplifier circuitry post-filter capacitor pin right channel, audio digital-to-analog converter post-filter capacitor pin left channel, audio digital-to-analog converter supply ground 3; audio digital-to-analog converter circuitry headphone (Auxiliary) output right channel headphone (Auxiliary) output left channel analog supply voltage 3; audio digital-to-analog converter loudspeaker (Main) output right channel loudspeaker (Main) output left channel line output left channel line output right channel digital supply voltage 2; digital circuitry
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
handbook, halfpage
PCLK 1 NICAM 2 ADDR1 3 SCL 4 SDA 5 VSSA1 6 VDDA1 7 Iref 8 P1 9 SIF2 10 Vref1 11 SIF1 12 ADDR2 13 VSSD1 14 VDDD1 15 CRESET 16 XTALO 17 XTALI 18 Vtune 19 P2 20 SYSCLK 21 SCK 22 WS 23 SDO2 24 SDO1 25 SDI2 26 SDI1 27 TEST1 28 MONOIN 29 TEST2 30 EXTIR 31 EXTIL 32
MGK106
64 VDDD2 63 LOR 62 LOL 61 MOL 60 MOR 59 VDDA3 58 AUXOL 57 AUXOR 56 VSSA3 55 PCAPL 54 PCAPR 53 Vref3 52 SCOL2 51 SCOR2 50 VSSA4 49 VSSD2
TDA9875
48 SCOL1 47 SCOR1 46 Vref2 45 CAPR1 44 CAPR2 43 VSSA2 42 CAPL2 41 CAPL1 40 Vref(n) 39 Vref(p) 38 VDDA2 37 SCIL2 36 SCIR2 35 VSSG 34 SCIL1 33 SCIR1
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
6 6.1 6.1.1 FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section SIF INPUT 6.1.5 FM IDENTIFICATION
TDA9875
Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz. 6.1.2 AGC
The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification. 6.1.6 NICAM DEMODULATION
The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen from Table 12 (subaddress 0). The AGC can be controlled via the I2C-bus. Details can be found in the I2C-bus register definitions (see Chapter 10). 6.1.3 MIXER
The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit/s. The NICAM demodulator performs DQPSK demodulation and feeds the resulting bitstream and clock signal onto the NICAM decoder and, for evaluation purposes, to PCLK (pin 1) and NICAM (pin 2). A timing loop controls the frequency of the crystal oscillator to lock the sampling rate to the symbol timing of the NICAM data. The polarity of the control signal is selectable to support applications in which external circuitry is used to boost the tuning voltage of the oscillator. 6.1.7 NICAM DECODER
The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus. When receiving NICAM programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrier-frequency loop. 6.1.4 FM AND AM DEMODULATION
The device performs all decoding functions in accordance with the "EBU NICAM 728 specification". After locking to the frame alignment word, the data is descrambled by applying the defined pseudo-random binary sequence; the device will then synchronize to the periodic frame flag bit C0. The status of the NICAM decoder can be read out from the NICAM status register by the user (see the I2C-bus register description in Section 10.4.2). The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM data and that the data is valid sound data. The C4 bit indicates that the sound conveyed by the FM mono channel is identical to the sound conveyed by the NICAM channel. The error byte contains the number of sound sample errors, resulting from parity checking, that occurred in the past 128 ms period. The Bit Error Rate (BER) can be calculated using the following equation; -5 bit errors BER = ---------------------- error byte x 1.74 x 10 total bits
An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
6.1.8 NICAM AUTO-MUTE
TDA9875
When the AM sound in NICAM L systems is demodulated in the 1st sound IF and the audio signal connected to the mono input of the TDA9875, the controlling microcontroller must implement the switching from NICAM reception to mono input, if auto-muting is desired. 6.1.9 CRYSTAL OSCILLATOR
This function is enabled by setting bit AMUTE LOW subaddress 14 (see Section 10.3.11). Upper and lower error limits may be defined by writing appropriate values to two registers in the I2C-bus section (subaddresses 16 and 17; see Sections 10.3.13 and 10.3.14). When the number of errors in a 128 ms period exceeds the upper error limit the auto-mute function will switch the output sound from NICAM to whatever sound is on the first sound carrier (FM or AM). When the error count is smaller than the lower error limit the NICAM sound is restored. The auto-mute function can be disabled by setting bit AMUTE HIGH. In this condition clicks become audible when the error count increases; the user will hear a signal of degrading quality. A decision to enable/disable the auto-muting is taken by the microcontroller based on an interpretation of the application control bits C1, C2, C3 and C4 and, possibly, any additional strategy implemented by the set maker in the microcontroller software.
A circuit diagram of the external components of the voltage-controlled crystal oscillator is illustrated in Fig.8 (see Chapter 12). 6.1.10 TEST PINS
Both test pins are active HIGH, in normal operation of the device they are wired to VSSD1. Test functions are for manufacturing tests only and are not available to customers. Without external circuitry these pads are pulled down to LOW level with internal resistors.
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dbook, full pagewidth
1998 Feb 13
2 2 2 LEVEL ADJUST from ADC 2 DC FILTER 2 4 LEVEL ADJUST I2S1 2 6 2 LEVEL ADJUST I2S2 2 8
6.2 Description of the DSP
Philips Semiconductors
Digital TV Sound Processor (DTVSP)
2
MATRIX
AUTOMATIC VOLUME LEVEL VOLUME SOFT-MUTE BASS/TREBLE BEEPER
SPATIAL PSEUDO VOLUME BASS/TREBLE BASS BOOST CONTOUR SOFT-MUTE BEEPER
2
LS
2 DIGITAL CROSSBAR SELECT 2
MATRIX
2
HP
LEVEL ADJUST AND MUTE MATRIX
2
I2S1
12
NICAM FM 2 DC FILTER ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS 2 FIXED DE-EMPHASIS 2 4
LEVEL ADJUST
2 10 2
LEVEL ADJUST AND MUTE MATRIX
2
I2S2
LEVEL ADJUST MATRIX
LEVEL ADJUST MATRIX
2
DAC
12 16 MONITOR SELECT PEAK DETECTION 1
I2C-bus
MGK108
Preliminary specification
TDA9875
Fig.3 DSP data flow diagram.
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
6.2.1 LEVEL SCALING 6.2.6 LOUDSPEAKER (MAIN) CHANNEL
TDA9875
All input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range of 15 dB. It is recommended to scale all input channels to be 15 dB below full-scale (-15 dB full-scale) under nominal conditions. 6.2.2 NICAM PATH
The matrix provides the following functions; forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. There are fixed coefficient sets for spatial settings of 30%, 40% and 52%. The Automatic Volume Level (AVL) function provides a constant output level of -23 dB full-scale for input levels between 0 dBFS and -29 dB full-scale. There are some fixed decay time constants to choose from, i.e. 2, 4 and 8 seconds. Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter. There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 Hz. Volume is controlled individually for each channel ranging from +24 dB to -83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Contour is adjustable between 0 dB and +18 dB with 1 dB resolution. Bass is adjustable between +15 dB and -12 dB with 1 dB resolution and treble is adjustable between 12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in dBs (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented coefficient set serves merely as an example on how to use this filter. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full-scale between 0 dB and -93 dB with a 3 dB step resolution. The beeper is not effected by mute.
The NICAM path has a switchable J17 de-emphasis. 6.2.3 FM (AM) PATH
A high-pass filter suppresses DC offsets from the FM demodulator due to carrier frequency offsets and supplies the monitor/peak function with DC values and an unfiltered signal, e.g. for the purpose of carrier detection. The de-emphasis function offers fixed settings for the supported standards (50 s, 60 s, 75 s and J17). An adaptive de-emphasis is available for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of 12(L + R) and R to L and R signals, of 12(L + R) and 12(L - R) to L and R signals or of channel 1 and channel 2 to L and R signals. 6.2.4 NICAM AUTO-MUTE
If NICAM is received and the signal quality becomes poor, the digital crossbar switch switches automatically to FM and switches the matrix to channel 1. The automatic switching between NICAM and channel 1 (FM or AM) reception depends on the NICAM bit error rate. The auto-mute function can be disabled via the I2C-bus. 6.2.5 MONITOR
This function provides data words from a number of locations of the signal processing paths to the I2C-bus interface (2 data bytes). Signal sources include the FM demodulator outputs, most inputs to the digital crossbar switch and the inputs to the loudspeaker channel of the ADC. Source selection and data read-out is performed via the I2C-bus. Optionally, the peak value can be measured instead of simply taking samples. The internally stored peak value is reset to zero when the data is read via the I2C-bus. The monitor function may be used, for example, for signal level measurements or carrier detection.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Soft-mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine masking. 6.2.7 HEADPHONE (AUXILIARY) CHANNEL
TDA9875
One example of how the feature interface can be used in a TV set is to connect an external Dolby Surround Pro Logic DSP, such as the SAA7710, to the I2S-bus ports. Outputs must be enabled and a suitable master clock signal for the DSP can be taken from pin SYSCLK. A stereo signal from any source will be output on one of the I2S-bus serial data outputs and the four processed signal channels will be entered at both I2S-bus serial data inputs. Left and right could then be output to the power amplifiers via the Main channel, centre and surround via the Auxiliary channel. 6.2.9 CHANNEL FROM THE AUDIO ANALOG-TO-DIGITAL
CONVERTER
The matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled individually for each channel in a range from +24 to -83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Bass is adjustable between +15 dB and -12 dB with 1 dB resolution and treble is adjustable between 12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for bass or treble is identical to the new bass or treble setting in dB (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full-scale between 0 dB and -93 dB with a 3 dB step resolution. The beeper is not effected by mute. Soft-mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine masking. 6.2.8 FEATURE INTERFACE
The signal level at the output of the ADC can be adjusted in a range of 15 dB with a 1 dB step resolution. The audio ADC itself is scaled to a gain of -6 dB. 6.2.10 CHANNEL TO THE ANALOG CROSSBAR PATH
Level adjust with control positions 0 dB, +3 dB, +6 dB and +9 dB. 6.2.11 DIGITAL CROSSBAR SWITCH (SEE Fig.6)
Input channels to the crossbar switch are from the audio ADC, I2S1, I2S2, FM path, NICAM path and from the loudspeaker channel path after matrix and AVL. Output channels comprise loudspeaker, headphone, I2S1, I2S2 and the audio DACs for line output and SCART. The I2S1 and I2S2 outputs also provide digital outputs from the loudspeaker and headphone channels, but without the beeper signals. 6.2.12 GENERAL
The feature interface comprises two I2S-bus input/output ports and a system clock output. Each I2S-bus port is equipped with level adjust facilities that can change the signal level in a 15 dB range in 1 dB steps. Outputs can be disabled to improve EMC performance. The I2S-bus output matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2.
There are a number of functions that can provide signal gain, e.g. volume, bass and treble control. Great care has to be taken when using gain with large input signals in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full-scale (-15 dB full-scale). This means that a volume setting of, say, +15 dB would just produce a full-scale output signal and not cause clipping, if the signal level is nominal. Sending illegal data patterns via the I2C-bus will not cause any changes of the current setting for the volume, bass, treble, bass boost and level adjust functions.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
6.2.13 EXPERT MODE
TDA9875
The TDA9875 provides a special expert mode that gives direct write access to the internal Coefficient RAM (CRAM) of the DSP. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses by means of the bass boost filter. However, this mode must be used with great care. More information on the functions of this device, such as filter structures, the number of coefficients per function, their default values, memory addresses, etc., can be made available on request. 6.2.14 Table 5 DSP CHARACTERISTICS DSP characteristics FUNCTION Bass control for loudspeaker and headphone output EXPERT MODE yes PARAMETER control range step resolution step resolution at frequency Treble control for loudspeaker and headphone output control range yes step resolution step resolution at frequency Contour for loudspeaker output yes Bass boost for loudspeaker output yes control range step resolution step resolution at frequency control range step resolution step resolution at frequency corner frequency Volume control for each separate channel in loudspeaker and headphone output Soft-mute for loudspeaker and headphone output Spatial effects Pseudo stereo Beeper additional to the signal in the loudspeaker and headphone channel control range no step resolution mute position at step no yes yes processing time anti-phase crosstalk positions 90 degree phase shift at frequency beep frequencies yes control range step resolution mute position at step AVL no step width VALUE -12 to +15 1 40 -12 to +12 1 14 0 to +18 1 40 0 to +20 2 20 350 -83 to +24 1 10101100 32 30, 40 and 52 150, 200 and 300 see Section 10.3.38 0 to -93 3 00100000 quasi continuously dB ms s Hz kHz dB dB ms % Hz UNIT dB dB Hz dB dB kHz dB dB Hz dB dB Hz Hz dB dB
AVL output level for an input level -23 between 0 dB and -29 dB (full-scale) attack time decay time constant 10 2, 4 and 8 14.5
General
no
-3 dB lower corner frequency of DSP 10 -1 dB bandwidth of DSP 15
1998 Feb 13
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
FUNCTION Level adjust I2S1 and I2S2 inputs Level adjust I2S1 and I2S2 outputs
EXPERT MODE yes
PARAMETER control range step resolution control range step resolution mute position at step control positions control range step resolution control range step resolution control range step resolution
VALUE -15 to +15 1 -15 to +15 1 00010000 0, 3, 6 and 9 +15 to -15 1 +15 to -15 1 +15 to -15 1
UNIT dB dB dB dB dB dB dB dB dB dB dB
yes no yes yes yes
Level adjust analog crossbar path Level adjust audio ADC outputs Level adjust NICAM path Level adjust FM path
6.3
Description of the analog audio section
handbook, full pagewidth
SCART 1
2
-3 dB
2
2
ANALOG MATRIX
2
3 dB 0 dB
2
SCART 1
2 SCART 2 2 -3 dB 2 ANALOG CROSSBAR SWITCH
ANALOG MATRIX
2
3 dB 0 dB
2
SCART 2
external mono
2
2
ANALOG MATRIX
2
3 dB 0 dB
2
Line output
2
D A
2
2
A D
2
NICAM FM I2S1 I2S2 I2S1 I2S2
2 2 2 2 2 2 DSP AND DIGITAL CROSSBAR SWITCH 2 D A 2 D A 2 2 Main
Auxiliary
MGK109
Fig.4 Block diagram for the audio section.
1998 Feb 13
16
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
6.3.1 ANALOG CROSSBAR SWITCH AND ANALOG MATRIX (see also Fig.6) 6.3.2 SCART INPUTS
TDA9875
There are a number of analog input and output ports with the TDA9875. Analog source selector switches are employed to provide the desired analog signal routing capability. The analog signal routing is performed by the analog crossbar switch section. A dual audio ADC provides the connection to the DSP section and a dual audio DAC provides the connection from the DSP section to the analog crossbar switch. The digital signal routing is performed by a digital crossbar switch. The basic signal routing philosophy of the TDA9875 is that each switch handles two signal channels at the same time, e.g. left and right, language A and B, directly at the source. Each source selector switch is followed by an analog matrix to perform further selection tasks, such as putting a signal from one input channel, say language A, to both output channels or for swapping left and right channels. The analog matrix provides the functions given in Table 6 (see also Fig.5). Table 6 Analog matrix functions MATRIX OUTPUT MODE LEFT OUTPUT 1 2 3 4 left input right input left input right input RIGHT OUTPUT right input left input left input right input
The SCART specification allows for a signal level of up to 2 V (RMS). Because of signal handling limitations, due to the 5 V supply voltage of the TDA9875, it is necessary to have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a -3 dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with maximum 1.4 V input), there are +3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. The input attenuator is realized by an external series resistor in combination with the input impedance, both of which form a voltage divider. With this voltage divider the maximum SCART signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. If it is known for certain applications that the input signal level is always below 1.4 V (RMS), the SCART inputs can be used without external resistors. 6.3.3 EXTERNAL AND MONO INPUTS
The 3 dB input attenuators are not required for the external and mono inputs, because those signal levels are under control of the TV designer. The maximum allowed input level is 1.4 V (RMS). By adding external series resistors, the external inputs can be used as an additional SCART input. 6.3.4 SCART OUTPUTS
handbook, halfpage
left input
right input
ANALOG MATRIX
left output right output
MGK110
The SCART outputs employ amplifiers with two gain settings. The gain can be set to +3 dB or to 0 dB via the I2C-bus. The +3 dB position is needed to compensate for the 3 dB attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be preferred [under the condition of 1.4 V (RMS) maximum input level]. The 0 dB position is needed, for example, for an external-to-SCART copy with 0 dB gain. 6.3.5 LINE OUTPUT
Fig.5 Analog matrix.
All switches and matrices are controlled via the I2C-bus. There is one restriction for switching signals at inputs and outputs for SCART 1 and SCART 2. At these ports, an input signal cannot be copied to its own output, i.e. it is not possible to make a copy from SCART 1 input to SCART 1 output.
The line output can provide an unprocessed copy of the audio signal in the loudspeaker channels. This can be either an external signal that comes from the dual audio ADC, or a signal from an internal digital audio source that comes from the dual audio DAC. The line output employs amplifiers with two gain settings. The +3 dB position is needed to compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for example, for non-attenuated external or internal digital signals (see Section 6.3.4).
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
6.3.6 LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS 6.3.9 STANDBY MODE
TDA9875
Signals from any audio source can be applied to the loudspeaker and to the headphone output channels via the digital crossbar switch and the DSP. 6.3.7 DUAL AUDIO DAC
The standby mode (subaddress 1, bit 5) disables most functions and reduces power dissipation. The analog crossbar switch and the SCART section remains operational and can be controlled by the I2C-bus to support copying of analog signals from SCART 1 to SCART 2 and vice versa. Unused internal registers may lose their information in standby mode. Therefore, the device needs to be initialized on returning to normal operation. This can be accomplished in the same way as after a power-on reset.
The TDA9875 contains three dual audio DACs, one for the connection from the DSP to the analog crossbar switch section and two for the loudspeaker and headphone outputs. Each of the three dual low-noise high-dynamic range DACs consists of two 15-bit DACs with current outputs, followed by a buffer operational amplifier. The audio DACs operate with four-fold oversampling and noise shaping. 6.3.8 DUAL AUDIO ADC
There is one dual audio ADC in the TDA9875 for the connection of the analog crossbar switch section to the DSP. The dual audio ADC consists of two bitstream 3rd-order sigma-delta audio ADCs and a high-order decimation filter.
1998 Feb 13
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andbook, full pagewidth
1998 Feb 13
SCART 1 SCART 2 SW4 ADC external LEVEL ADJUST mono FM/AM part
Philips Semiconductors
Digital TV Sound Processor (DTVSP)
SW5
DIGITAL MATRIX
AUTOMATIC VOLUME LEVEL
LOUDSPEAKER CHANNEL PROCESSING
Main DAC
SW6
DIGITAL MATRIX
HEADPHONE CHANNEL PROCESSING
Auxiliary DAC
SW7
DIGITAL MATRIX
LEVEL ADJUST
I2S1 I2S2
19
FM/AM DEMODULATOR
ADAPTIVE DE-EMPHASIS
FIXED DE-EMPHASIS
STEREO DECODER
LEVEL ADJUST
SW8
DIGITAL MATRIX
LEVEL ADJUST
SW3
ANALOG MATRIX
BUFFER 0/+3 dB
Line
NICAM part
NICAM DECODER
DE-EMPHASIS
LEVEL ADJUST
SW1 LEVEL ADJUST
ANALOG MATRIX
BUFFER 0/+3 dB
SCART 1
I2S1
SW9
DIGITAL MATRIX
LEVEL ADJUST
DAC SW2 ANALOG MATRIX BUFFER 0/+3 dB SCART 2
Preliminary specification
I2S2
LEVEL ADJUST
MGK111
TDA9875
Fig.6 Audio signal flow diagram.
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VDD IIK IOK IO IDDD, ISSD IDDA, ISSA Ilu(prot) P/out Ptot Tstg Tamb Ves PARAMETER DC supply voltage voltage differences between two VDD pins DC input clamping diode current DC output clamping diode current (output type 4 mA) DC output source or sink current (output type 4 mA) DC VDD or VSS current per digital supply pin DC VDD or VSS current per analog supply pin latch-up protection power dissipation per output total power dissipation storage temperature operating ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1.5 k. 2. Machine model: C = 200 pF; L = 0.75 H; R = 0 . 8 THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 31 VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V -0.5 V < VO < VDD + 0.5 V CONDITIONS - - - - - - 100 - - -55 -20 2000 200 MIN. -0.5
TDA9875
MAX. +6.5 550 10 20 20 100 50 - 100 1.3 +125 +70 - -
UNIT V mV mA mA mA mA mA mA mW W C C V V
UNIT K/W
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
9 CHARACTERISTICS VDD = 5 V; Tamb = 25 C; settings in accordance with B/G standard; FM deviation 50 kHz; fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with "EBU specification"; 1 k measurement source resistance for AF inputs; unless otherwise specified. SYMBOL Digital supplies VDDD1 VSSD1 IDDD1 VDDD2 VSSD2 IDDD2 digital supply voltage 1 digital supply ground 1 digital supply current 1 digital supply voltage 2 digital supply ground 2 digital supply current 2 VDDD2 = 5.5 V VDDD2 = 5.0 V Demodulator supplies and references VDDA1 VSSA1 IDDA1 Vref1 Iref1(sink) VDDA2 VSSA2 IDDA2 VDDA3 VSSA3 IDDA3 VSSA4 VSSG Vref2 analog supply voltage for demodulator part analog ground for demodulator part analog supply current for demodulator part analog reference voltage for demodulator part Vref1 sink current analog supply voltage for audio ADC part analog ground for audio ADC part analog supply current for audio ADC part analog supply voltage for audio DAC part analog ground for audio DAC part analog supply current for audio DAC part analog ground for operational amplifier ground, guard rings for analog-to-digital circuitry reference voltage for audio ADCs referenced to VDDA2/VSSA2 VDDA = 5.5 V VDDA = 5.0 V VDDA = 5.5 V VDDA = 5.0 V referenced to VDDA1/VSSA1 4.75 - 20 19 35 170 5.0 0.0 26 24 50 220 5.5 - 31 28 65 260 V V mA mA % A VDDD1 = 5.5 V VDDD1 = 5.0 V 4.75 - 65 55 4.75 - 50 45 5.0 0.0 80 70 5.0 0.0 65 55 5.5 - 95 85 5.5 - 80 65 V V mA mA V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Audio supplies and references 4.75 - 11 10 4.75 - VDDA = 5.5 V; digital silence 9 VDDA = 5.0 V; digital silence 8 - - - 5.0 0.0 14 13 5.0 0.0 12 11 0.0 0.0 50 5.5 - 17 16 5.5 - 14 13 - - - V V mA mA V V mA mA V V %
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
SYMBOL ZVref2-VDDA2 ZVref2-VSSA2 Vref3 ZVref3-VDDA3 ZVref3-VSSA3
PARAMETER impedance Vref2 to VDDA2 impedance Vref2 to VSSA2 reference voltage for audio DAC and operational amplifier impedance Vref3 to VDDA3 impedance Vref3 to VSSA3
CONDITIONS - - referenced to VDDA3/VSSA3 - - -
MIN. 20 20 50 20 20
TYP.
MAX. - - - - -
UNIT k k % k k
Digital inputs and outputs INPUTS
CMOS level input, high drive, pull-down (pins TEST1 and TEST2)
VIL VIH Ci Zi VIL VIH Vhys Ci Zi LOW level input voltage HIGH level input voltage input capacitance input impedance - 3.0 - - - 3.0 - - - - - - 50 - - 0.33VDDD - 50 1.6 - 10 - 1.6 - - 10 - V V pF k
CMOS level input, hysteresis, high drive, pull-up (pin CRESET)
LOW level input voltage HIGH level input voltage hysteresis voltage input capacitance input impedance V V V pF k
INPUTS/OUTPUTS
I2C-bus level input with Schmitt trigger, open-drain output stage (pins SCL and SDA)
VIL VIH VHYS ILI Ci VOL CL LOW level input voltage HIGH level input voltage hysteresis voltage input leakage current input capacitance LOW level output voltage load capacitance active pull-up passive pull-up - 3.0 - - - - - - - - 0.33VDDD - - - - - 1.6 - - 10 10 0.5 400 200 V V V A pF V pF pF
TTL/CMOS level, high drive, 4 mA 3-state output stage, pull-up (pins PCLK, NICAM, ADDR1, ADDR2, P1, P2, SCK, WS, SDO1, SDO2, SDI1 and SDI2)
VIL VIH Ci VOL VOH CL Zi LOW level input voltage HIGH level input voltage input capacitance LOW level output voltage HIGH level output voltage load capacitance input impedance IOL = 3 mA IOH = -3 mA active pull-up - 2.0 - - 2.9 - - - - - - - - 50 0.8 - 10 0.5 - 50 - V V pF V V pF k
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
SYMBOL OUTPUTS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
4 mA 3-state output stage (pin SYSCLK)
VOL VOH CL ILIZ VSIFmax(rms) VSIFmin(rms) AGC fi Ri Ci fFM fFM(FS) C/NFM LOW level output voltage HIGH level output voltage load capacitance 3-state leakage current Vi = 0 to VDDD IOL = 2 mA IOH = -2 mA - 2.9 - - - - - 4 10 - B/G standard; THD < 1% terrestrial FM; level adjust 0 dB NFM bandwidth = 6 MHz; white noise for S/N = 40 dB; "CCIR468"; quasi peak Nc bandwidth = 6 MHz; bit error rate = 10-3; white noise fi = 4 to 9.2 MHz 100 150 - - - - - 0.5 - 50 10 - - - 9.2 16 11 - - - V V pF A
SIF1 and SIF2 analog inputs maximum composite SIF input voltage (RMS value) minimum composite SIF input voltage (RMS value) AGC range input frequency input resistance input capacitance FM deviation FM deviation full-scale level FM carrier C/Nc ratio 250 21 21 - 13 7.5 - - 77 mV mV dB MHz k pF kHz kHz dB FM ------------Hz
C/NN
NICAM carrier C/Nc ratio
-
66
-
dB N ---------Hz dB
ct
crosstalk attenuation input channel
50
-
-
Demodulator performance THD + N total harmonic distortion plus noise from FM source to any output; Vo = 1 V (RMS) from NICAM source to any output; Vo = 1 V (RMS) S/N signal-to-noise ratio - - 0.3 0.1 65 0.5 0.3 - % % dB
SC1 from FM source to any 61 output; Vo = 1 V (RMS), TIMPOL bit HIGH SC2 from FM source to any 57 output; Vo = 1 V (RMS), TIMPOL bit HIGH NICAM source; Vo = 1 V (RMS)
60
-
dB
NICAM in accordance with "EBU specification"; note 2
1998 Feb 13
23
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
SYMBOL B-3
PARAMETER -3 dB bandwidth
CONDITIONS from FM source to any output from NICAM source to any output
MIN. 14.5 14.5 65 40 15 15 70 45 -
TYP.
MAX. - - - - -
UNIT kHz kHz dB dB dB
ct cs(stereo) AM
crosstalk attenuation stereo channel separation AM suppression for FM
from SIF1 or SIF2 to any output
AM: 1 kHz, 50 30% modulation; reference: 1 kHz, 50 kHz deviation
DEPD S/NAM
de-emphasis AM demodulation SIF level 100 mV (RMS); 54% AM; 1 kHz AF; "CCIR468"; quasi peak
50 s, 60 s, 75 s, J17, adaptive de-emphasis - 36 - dB
IDENTIFICATION FOR FM SYSTEMS modp C/Np hystun fident pilot modulation for identification pilot sideband C/N for identification start hysteresis identification window B/G stereo slow mode medium mode fast mode B/G dual slow mode medium mode fast mode tident(on) total identification time ON slow mode medium mode fast mode tident(off) total identification time OFF slow mode medium mode fast mode Analog audio inputs MONO INPUT Vi(nom)(rms) Vi(clip)(rms) Ri nominal level input voltage (RMS value) clipping level input voltage (RMS value) input resistance note 3 THD < 3%; note 4 note 4 - 1250 28 500 1400 35 - - 42 mV mV k 273.44 272.07 270.73 - - - - - - - - - - - - - - - 274.81 276.20 277.60 2 1 0.5 2 1 0.5 Hz Hz Hz s s s s s s 116.85 116.11 114.65 - - - 118.12 118.89 120.46 Hz Hz Hz 25 - - 50 32 - 75 - 2 % dB -----Hz dB
1998 Feb 13
24
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
SYMBOL
PARAMETER
CONDITIONS -3 dB divider with external 15 k resistor; notes 3 and 5 -3 dB divider with external 15 k resistor; THD < 3%; notes 4 and 5 note 4 -
MIN.
TYP.
MAX. -
UNIT
SCART AND EXTERNAL INPUTS Vi(nom)(rms) nominal level input voltage at input pin (RMS value) clipping level input voltage at input pin (RMS value) input resistance 350 mV
Vi(clip)(rms)
1250
1400
-
mV
Ri
28
35
42
k
Analog audio outputs LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS Vo(clip)(rms) Ro RL(AC) RL(DC) CL Voffset(DC) mute clipping level output voltage (RMS value) output resistance AC load resistance DC load resistance output load capacitance static DC offset voltage mute suppression nominal input signal from any source; fi = 1 kHz; note 3 from any source fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 F; signal from I2S-bus THD < 3% 1400 150 10 10 - - 80 - 250 - - 10 30 - - 375 - - 12 70 - mV k k nF mV dB
Gro(main,aux)
roll-off gain at 14.5 kHz for Main and Auxiliary channels
-3 40
-2 45
- -
dB dB
PSRRmain,aux power supply ripple rejection for Main and Auxiliary channels
SCART OUTPUTS AND LINE OUTPUT Vo(nom)(rms) Vo(clip)(rms) Ro RL(AC) RL(DC) CL Voffset(DC) mute nominal level output voltage (RMS value) clipping level output voltage (RMS value) output resistance AC load resistance DC load resistance output load capacitance static DC offset voltage mute suppression output amplifiers at +3 dB position nominal input signal from any source; fi = 1 kHz; note 3 +3 dB amplification; note 3 THD < 3% - - 150 10 10 - - 80 500 1400 250 - - - 30 - - - 375 - - 2.5 50 - mV mV k k nF mV dB
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
SYMBOL Bline
PARAMETER line bandwidth
CONDITIONS from SCART, external, Auxiliary and mono sources; -3 dB bandwidth from DSP sources; -3 dB bandwidth
MIN. 20 -
TYP.
MAX. -
UNIT kHz
14.5 40
- 45
- -
kHz dB
PSRRline
power supply ripple rejection
fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 F; signal from I2S-bus
Audio performance THD + N total harmonic distortion plus noise Vi = Vo = 1 V (RMS); fi = 1 kHz; bandwidth 20 Hz to 15 kHz; note 1 from any analog audio input to I2S-bus from I2S-bus to any analog audio output SCART-to-SCART copy SCART-to-Main copy S/N signal-to-noise ratio reference voltage Vo = 1.4 V (RMS); fi = 1 kHz; "CCIR468"; quasi peak; note 1 from any analog audio input to I2S-bus from I2S-bus to any analog audio output SCART-to-SCART copy SCART-to-Main copy ct crosstalk attenuation between any analog input pairs; fi = 1 kHz between any analog output pairs; fi = 10 kHz cs channel separation between left and right of any input pair between left and right of any output pair GA from SCART-to-SCART with -3 dB input voltage divider output amplifier in +3 dB position; Rext = 15 k 10% output amplifier in 0 dB position; Rext = 15 k 10% from external input to loudspeaker Rext = 15 k 10%; note 1 73 78 78 73 70 65 65 60 -1.5 77 90 90 77 - - - - 0 - - - - - - - - +1.1 dB dB dB dB dB dB dB dB dB - - - - 0.1 0.1 0.1 0.2 0.3 0.3 0.3 0.5 % % % %
-4.5
-3.0
-1.9
dB
-1.5
0
+1.5
dB
1998 Feb 13
26
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCXO and clock generation VCXO
Crystal input
Ci Vbias(DC) input capacitance DC bias voltage Ri = 100 k - 3.5 - 2.0 16.6 - - - - - CL changed from 18 to 16 pF at nominal frequency - - 2RR -20 - across temperature range - - - 3.63 10 3.7 - 2.8 18.8 pF V
Crystal output
Vosc(p-p) Vbias(DC) Gm oscillation amplitude (peak-to-peak value) DC bias voltage mutual conductance at 24.576 MHz output capacitance 1.4 2.4 17.6 - 24.576 20 20 - 25 - - +25 - - - V V mA -------V pF
Co fxtal CL C1 C0 pull
10 - - - 7 -
CRYSTAL SPECIFICATION (FUNDAMENTAL MODE) crystal frequency load capacitance series capacitance parallel capacitance pulling sensitivity MHz pF fF pF 10 ----------pF C 10-6 10-6 10 ----------year
-6 -6
RR RN T XJ XD XA
equivalent series resistance equivalent series resistance of unwanted mode temperature range adjustment tolerance drift ageing
30 - +70 30 30 5
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Notes to the characteristics
TDA9875
1. ADC level adjust = +6 dB, all other level adjusts = 0 dB, if external -3 dB divider is used set output buffer gain to +3 dB, tone control to 0 dB, AVL off and volume control to 0 dB. 2. Due to companding, the quantization noise of the NICAM system limits signal-to-noise ratio to 62 dB (unweighted; RMS value). 3. Definition of nominal levels: The full-scale level for analog audio signals is VFS = 1.4 V (RMS). The nominal level at the digital crossbar switch is defined at -15 dB (full-scale). a) Audio input nominal levels: SCART: 350 mV (at pin); -12 dB (full-scale) external, mono: 500 mV; -9 dB (full-scale) b) FM/AM path nominal (maximum) levels: system M: 15 kHz deviation; -23.7 dB (full-scale) system B/G, D/K, I: 27 kHz deviation; -18.6 dB (full-scale) SAT stereo (maximum): 50 kHz deviation; -13.3 dB (full-scale) SAT mono (maximum): 85 kHz deviation; -8.7 dB (full-scale) AM: 54% modulation; full-scale SIF ADC; -20 dB (full-scale) c) NICAM path nominal (maximum) levels: system B/G: -18.2 dB (full-scale) system I: -22.8 dB (full-scale) maximum level: 0.0 dB (full-scale). 4. If the supply voltage for the TDA9875 is switched off, because of the ESD protection circuitry, all audio input pins are short-circuited. To avoid a short-circuit at the SCART inputs a 15 k resistor (-3 dB divider) has to be used. 5. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the 5 V supply voltage for the TDA9875, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve SCART-to-SCART copies with 0 dB gain, there are +3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. The attenuator is realized by an internal resistor that works together with an external series resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. To avoid clipping, the +3 dB gain must not be used if the SCART input signal is larger than 1.4 V (RMS).
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10 I2C-BUS CONTROL 10.1 Introduction 10.2 Power-up state
TDA9875
At power-up the device is in the following state: * All outputs muted * No sound carrier frequency loaded * General-purpose I/O pins ready for input (HIGH) * Input SIF1 selected with: - AGC on - Small hysteresis. * Demodulators for both sound carriers set to FM with: - Identification for B/G, D/K, response time 1 s - Level adjust set to 0 dB - De-emphasis 50 s - Matrix set to mono. * Main channel set to FM input with: - Spatial off - Pseudo off - AVL off - Volume mute - Bass flat - Treble flat - Contour off - Bass boost flat. * Auxiliary channel set to FM input with: - Volume mute - Bass flat - Treble flat. * Feature interface all outputs off * Beeper off * Monitoring of carrier 1 FM demodulator DC output. After power-up a device initialization has to be performed via the I2C-bus to put the TDA9875 into the proper mode of operation, in accordance with the desired TV standard, audio control settings, etc.
The TDA9875 is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers. Status information can be read from an array of registers to enable the controlling microcontroller determine whether any action is required. The device has an I2C-bus slave transceiver, in accordance with the fast-mode specification, with a maximum speed of 400 kbits/s. Information concerning the I2C-bus can be found in brochure "I2C-bus and how to use it" (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or complementary functions, there are four possible slave addresses available which can be selected by pins ADDR1 and ADDR2 (see Table 7). Table 7 Possible slave addresses ADDR1 0 1 0 1 SLAVE ADDRESS A6 TO A0 1011000 1011001 1011010 1011011
ADDR2 0 0 1 1
The I2C-bus interface remains operational in the standby mode of the TDA9875 to allow control of the analog source selectors with regard to SCART-to-SCART copying. The device will not respond to a `general call' on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master. The data transmission between the microcontroller and the other I2C-bus controlled ICs is not disturbed when the supply voltage of the TDA9875 is not connected.
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3 Slave receiver mode
TDA9875
As a slave receiver, the TDA9875 provides 46 registers for storing commands and data. These registers are accessed via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location. Table 8 S Table 9 I2C-bus; slave address, subaddress and data format SLAVE ADDRESS Explanation of Table 8 BIT S SLAVE ADDRESS 0 ACK SUBADDRESS DATA P START condition 7-bit device address data direction bit (write to device) acknowledge address of register to write to data byte to be written into register STOP condition FUNCTION 0 ACK SUBADDRESS ACK DATA ACK P
It is allowed to send more than one data byte per transmission to the TDA9875. In this event, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with ACK (acknowledge). There is no `wrap-around' of subaddresses. Commands and data are processed as soon as they have been completely received. Functions requiring more than one byte will, thus, be executed only after all bytes for that function have been received. Should the transmission is terminated (STOP condition) before all bytes have been received, the incomplete data for that function are ignored. Table 10 Format for a transmission employing auto-increment of subaddresses S Note 1. n data bytes with auto-increment of subaddresses. Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the functions of volume, bass, treble control, bass boost and level adjust. Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will not then be executed. SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA BYTE A(1) DATA ACK P
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 11 Overview of the slave receiver registers (note 1) SUBADDRESS (DECIMAL) MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 X c p f f f f f f c d X X X X X l u m g X X X s X X v v X X X X v v X X X X X c X f f f f f f c d X X X X X l u m m g g g s m X v v X X X m v v X X X m X c X f f f f f f c d X X X c X l u m m m m m s m s v v X X X m v v X X X m DATA FUNCTION LSB g c m f f f f f f X d X l l c l l u m m m m m l m s v v c b t m v v b t c m g c m f f f f f f c d X l l X l l u m g X X X l X p v v c b t X v v b t c X g c s f f f f f f c d m l l X l l u m s s s X l s p v v c b t s v v b t c s g c s f f f f f f c d m l l c l l u m s s s X l s a v v c b t s v v b t c s g c s f f f f f f c d m l l c l l u m s s s s l s a v v c b t s v v b t c s
TDA9875
AGC gain selection (ignored, if AGC off) general configuration monitor select, peak detector on/off carrier 1 frequency; MS part carrier 1 frequency carrier 1 frequency; LS part carrier 2 frequency; MS part carrier 2 frequency carrier 2 frequency; LS part demodulator configuration FM de-emphasis FM matrix channel 1 output level adjust channel 2 output level adjust NICAM configuration NICAM output level adjust NICAM lower error limit NICAM upper error limit audio mute control DAC output select SCART 1 output select SCART 2 output select line output select ADC output select Main channel select audio effects (AVL, pseudo, spatial) volume control, Main left volume control, Main right contour control, Main bass control, Main treble control, Main Auxiliary channel select volume control, Auxiliary left volume control, Auxiliary right bass control, Auxiliary treble control, Auxiliary feature interface configuration I2S1 output select
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
SUBADDRESS (DECIMAL) MSB 38 39 40 41 42 43 44 45 Note X X X X X X X b X X m X X X X b X X m X X X v b i
DATA FUNCTION LSB i o X i o X v b i o s i o f v b i o s i o f v b i o s i o f v b I2S1 input level adjust I2S1 output level adjust I2S2 output select I2S2 input level adjust I2S2 output level adjust beeper frequency beeper volume, Main and Auxiliary bass boost, Main left and right o m i o X v b
1. X indicates bits that have not yet been assigned to a function. Their meaning is `don't care'. They should be written as a zero. The following sub-sections provide a detailed description of the slave receiver registers: 10.3.1 AGC GAIN REGISTER
10.3.1.1
Description
If the automatic gain control function is switched off in the General Configuration Register, the contents of this register will define a fixed gain of the AGC stage. The input voltages given are meant to generate a full-scale output from the SIF ADC. If automatic gain control is on, the contents of this register is ignored. It should be noted that the input voltages should be considered as approximate target values.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.1.2 Definition
TDA9875
Table 12 Subaddress 0 (notes 1 and 2) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 SIF INPUT VOLTAGE [mV (RMS)] 240 214 195 176 159 145 131 119 107 99 90 82 76 70 65 60 55 51 48 45 42 39 36 34 32 30 29 27 25 24 23 22
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.2 GENERAL CONFIGURATION REGISTER
TDA9875
10.3.2.1
Description
Table 13 Description of Table 14 NAME SIFSEL AGCOFF HIGH/LOW HIGH LOW HIGH LOW AGCSLOW HIGH LOW INIT HIGH Pin SIF1 (terrestrial TV) is selected. Forces the AGC block to a fixed gain as defined in the AGC gain register. The automatic gain control function is enabled and the contents of the AGC gain register is ignored. A longer decay time and larger hysteresis are selected for input signals with strong video modulation (intercarrier). This bit only has an effect when bit AGCOFF = 0. Selects normal attack and decay times for the AGC and a small hysteresis. Causes initialization of TDA9875 to its default settings. This has the same effect as a power-on reset. If there is a conflict between the default settings and any bit set HIGH in this register, the bits of this register have priority over the corresponding default setting. This bit is automatically reset to LOW after initialization. When set LOW, the TDA9875 is in its normal mode of operation. Puts the TDA9875 into the standby mode. Most functions are disabled and power dissipation is somewhat reduced, but the analog selectors/matrices remain operational to support analog copying from SCART 1 to SCART 2 and vice versa. The TDA9875 is in its normal mode of operation. On return from standby mode, the device is in its power-on reset mode and needs to be re-initialized. These bits control the general purpose input/output pins. The contents of these bits is written directly to the corresponding pins. If input is desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input from the pins is reflected in the device status register (see Section 10.4, subaddress 0). P1OUT is recommended to be used for switching an SIF trap for the adjacent picture carrier in designs that employ such a trap. FUNCTION Selects pin SIF2 for input (recommended for satellite tuner).
LOW STDBY HIGH
LOW P1OUT, P2OUT -
10.3.2.2
Definition
Table 14 Subaddress 1 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 11000000. NAME P2OUT P1OUT STDBY INIT X AGCOFF SIFSEL general purpose I/O pin 2 general purpose I/O pin 1 stand-by mode on/off initialize to defaults (as reset) don't care AGC on/off SIF input select DESCRIPTION
AGCSLOW AGC decay time
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.3 MONITOR SELECT REGISTER
TDA9875
10.3.3.1
Description
This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be monitored. Peak level refers to the magnitude of the maximum excursion of a signal. Data can be read-out in the I2C-bus slave transmitter mode (see Section 10.4, subaddresses 5 and 6). Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in FM mode, while magnitude is supplied in AM mode. Table 15 Description of bit PEAKMON NAME PEAKMON HIGH/LOW HIGH LOW the last sample will be supplied FUNCTION selects the peak level of a source to be monitored
10.3.3.2
Definition
Table 16 Subaddress 2 (notes 1, 2 and 3) MSB B7 PEAKMON Notes 1. X = don't care. 2. PEAKMON is described in Section 10.3.3.1. 3. The default setting at power-up is 00000000. Table 17 Signal source (note 1) B2 0 0 0 0 1 1 1 1 Note 1. The term `crossbar' refers to the digital selector, where level-adjusted signals from various sources are available. B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 SIGNAL SOURCE DC output of FM demodulator audio magnitude/phase, FM demodulator output crossbar input from FM/AM channel crossbar input from NICAM channel crossbar input from I2S1 channel crossbar input from I2S2 channel crossbar input from audio ADC channel input to Main channel DAC (without beeper) B6 X B5 X B4 B3 B2 B1 see Table 17 see Table 18 LSB B0
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 18 Monitor output B4 0 0 1 B3 0 1 0 MONITOR OUTPUT L input + R input -----------------------------------------2 L input (channel 1, respectively) R input (channel 2, respectively) Table 19 Subaddresses 3 to 5 BIT 7 (MSB) 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Where: Data = 24-bit frequency control word fmix = desired sound carrier frequency fclk = 12.288 MHz (clock frequency of mixer) 224 = 16777216 (number of steps in a 24-bit word size). Example: A 5.5 MHz sound carrier frequency will be generated by sending the following sequence of data bytes to the TDA9875 (data = 7509333 in decimal notation or 729555 in hex): 01110010 10010101 01010101. As three bytes are required to define a carrier frequency, execution of this command starts only after all bytes have been received. If an error occurs, e.g. a premature STOP condition, partial data for this function is ignored. The default setting at power-up is 00000000 for all three bytes. 6 5 4 3 2 1 0 (LSB) 10.3.5
TDA9875
SUBADDRESSES
3
10.3.3.3
Note
By reading out Level Read-out Registers (subaddresses 5 and 6, see Section 10.4), the current peak level will be reset. 10.3.4 CARRIER 1 FREQUENCY REGISTER
10.3.4.1
Description
The three bytes together constitute a 24-bit frequency control word to represent the sound carrier (i.e. mixer) frequency in accordance with the following formula: f mix 24 data = -------- x 2 f clk
4
5
CARRIER 2 FREQUENCY REGISTER
10.3.5.1
Description
Same as for sound carrier 1. If the carrier 2 frequency register is used, it will be for either the second FM sound carrier of a terrestrial or satellite FM program or the NICAM sound carrier.
10.3.4.2
Definition
10.3.5.2
Definition
Most significant part at subaddress 3.
Subaddresses 6 to 8. Same as for sound carrier 1, except for subaddresses used.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.6 DEMODULATOR CONFIGURATION REGISTER
TDA9875
10.3.6.1
Definition
Table 20 Subaddress 9 (note 1; see Table 23) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 00000000. Table 21 Channel 2 receive mode (see Table 20) B3 0 0 1 Table 22 Identification mode (see Table 20) B7 0 0 1 1 B6 0 1 0 1 IDENT MODE slow medium fast off/reset B2 0 1 0 CHANNEL 2 FM AM NICAM NAME IDMOD1 IDMOD0 IDAREA X CH2MOD1 CH2MOD0 CH1WIDE CH1MODE channel 1 bandwidth channel 1 receive mode application area for FM identification don't care channel 2 receive mode DESCRIPTION response time for FM sound mode identification
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.6.2 Description
TDA9875
Table 23 Description of subaddress 9 (notes 1 and 2) NAME CH1MODE CH1WIDE HIGH/LOW HIGH LOW HIGH FUNCTION Selects the hardware for the first sound carrier to operate in AM mode. FM mode is assumed. This applies to both terrestrial and satellite FM reception. Switches the decimation filters for the first sound carrier to a wide bandwidth, so that the main sound carrier of a satellite channel with its larger deviation can be handled without additional distortion. The bandwidth is narrow to cope with the intermodulation requirements of FM stereo. These bits control the hardware for the second sound carrier in accordance with the truth Table 21. The NICAM mode employs a wider bandwidth of the decimation filters than the FM mode. Selects FM identification frequencies in accordance with the specification for Korea. Frequencies for Europe are selected (B/G and D/K standard). These bits define the response time after which a sound mode identification result may be expected. The longer the time, the more reliable the identification.
LOW CH2MOD0, CH2MOD1 IDAREA IDMOD0, IDMOD1 Notes -
HIGH LOW -
1. It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial 2-carrier sound. 2. Switching the identification off will reset the associated hardware to a defined state. 10.3.7 FM DE-EMPHASIS REGISTER
10.3.7.1
Description
This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2. In the event of FM stereo reception, both groups must be set to the same characteristics.
10.3.7.2
Definition
Table 24 Subaddress 10 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 00000000. ADEEM1 adaptive de-emphasis on/off time constant selection for FM de-emphasis NAME ADEEM2 adaptive de-emphasis on/off time constant selection for FM de-emphasis DESCRIPTION
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 25 De-emphasis B6 and B2 0 0 0 0 1 B5 and B1 0 0 1 1 0 B4 and B0 0 1 0 1 0 50 s (Europe) 60 s 75 s (M standard) J17 off DE-EMPHASIS
TDA9875
Table 26 Description of bits ADEEM1 and ADEEM2 (note 1) NAME ADEEM1, ADEEM2 Note 1. The FM de-emphasis gain is 0 dB at 40 Hz. 10.3.8 FM MATRIX REGISTER HIGH/LOW HIGH LOW FUNCTION Activates the adaptive de-emphasis function, which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 s. The adaptive de-emphasis is off.
10.3.8.1
Description
This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received carrier and the related sound mode identification. For the dematrixing, it is assumed that the output from sound carrier 1 is on channel L input.
10.3.8.2
Definition
Table 27 Subaddress 11 (notes 1 and 2) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. Table 28 Description of Subaddress 11 (bits B2 to B0) B2 0 0 0 0 1 1 B1 0 0 1 1 0 0 B0 0 1 0 1 0 1 L OUTPUT L input R input L input R input 2L input - R input L input + R input -----------------------------------------2 R OUTPUT L input R input R input L input R input L input - R input -----------------------------------------2 MODE mono 1 mono 2 dual dual swapped stereo Europe stereo Korea B6 X B5 X B4 X B3 X B2 B1 see Table 28 LSB B0
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.9 CHANNEL 1 OUTPUT LEVEL ADJUST REGISTER
TDA9875
10.3.9.1
Description
This register is used to correct for standard and station-dependent differences of signal levels. Table 29 applies to sound carrier 1.
10.3.9.2
Definition
Table 29 Subaddress 12 (notes 1 and 2) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 1998 Feb 13 40 B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.10 CHANNEL 2 OUTPUT LEVEL ADJUST REGISTER
TDA9875
10.3.10.1 Description
This register is used to correct for standard and station-dependent differences of signal levels. Table 30 applies to sound carrier 2 in its FM and AM modes. In the event of FM stereo or FM dual language reception, channels 1 and 2 should be adjusted to the same level.
10.3.10.2 Definition
Table 30 Subaddress 13 (notes 1 and 2) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
MSB B7 X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 10.3.11 NICAM CONFIGURATION REGISTER B6 X X X B5 X X X B4 1 1 1 B3 0 0 0 B2 0 0 0 B1 1 0 0
LSB B0 0 1 0
GAIN SETTING (dB) -14 -15 mute
10.3.11.1 Definition
Table 31 Subaddress 14 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 00000000. NAME X X TIMPOL DOUTEN X X NDEEM AMUTE don't care don't care timing loop polarity data output enable don't care don't care de-emphasis on/off auto-muting on/off DESCRIPTION
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.11.2 Description
Table 32 Description of Table 31 (notes 1, 2 and 3) NAME AMUTE HIGH/LOW HIGH LOW NDEEM DOUTEN HIGH LOW HIGH LOW TIMPOL HIGH FUNCTION
TDA9875
Automatic muting is disabled. This bit has only an effect when the second sound carrier is set to NICAM. enables the automatic switching between NICAM and the program on the first sound carrier (i.e. FM mono or AM), dependent on the NICAM bit error rate switches the NICAM J17 de-emphasis off switches the NICAM J17 de-emphasis on enables the output of the NICAM serial data stream from the DQPSK demodulator and of the associated clock, PCLK both outputs will be 3-stated Inverts the polarity. This feature can be used to compensate for the phase shift that is introduced by an external inverting amplifier at the pin Vtune. Such an amplifier could be used to provide a larger tuning voltage swing for the VCXO. sets the NICAM timing loop to normal polarity
LOW Notes
1. The decision of whether auto-muting is permitted shall be taken by the controlling microcontroller based on information contained in the TDA9875's status registers. Thus, it depends on the strategy implemented in the software whether the auto-mute function is in accordance with "NICAM 728 ETS Revised for Data Applications" or any other preference. 2. The NICAM de-emphasis gain is 0 dB at 40 Hz. 3. In FM mode of sound carrier 2, the TIMPOL bit can be used to switch pin Vtune HIGH or LOW. 10.3.12 NICAM OUTPUT LEVEL ADJUST REGISTER
10.3.12.1 Description
This register is used to correct for standard and station-dependent differences of signal levels. Table 33 applies to both NICAM sound outputs.
10.3.12.2 Definition
Table 33 Subaddress 15 (notes 1 and 2) MSB B7 X X X X X X X X X B6 X X X X X X X X X B5 X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 B2 1 1 1 1 0 0 0 0 1 B1 1 1 0 0 1 1 0 0 1 LSB B0 1 0 1 0 1 0 1 0 1 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
MSB B7 X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 10.3.13 NICAM LOWER ERROR LIMIT REGISTER B6 X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
GAIN SETTING (dB) +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
10.3.13.1 Description
When the auto-mute function is enabled (bit AMUTE in the NICAM configuration register) and the NICAM bit error count is lower than the value contained in this register, the NICAM signal is reselected for reproduction, see Section 10.3.14.
10.3.13.2 Definition
Table 34 Subaddress 16 (notes 1 and 2) MSB B7 Notes 1. The default setting at power-up is 00010100. 2. The lower bit error rate limit subaddress 16 x 1.74 x 10-5. 1998 Feb 13 44 B6 B5 B4 B3 B2 B1 LSB B0
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.14 NICAM UPPER ERROR LIMIT REGISTER
TDA9875
10.3.14.1 Description
When the auto-mute function is enabled (bit AMUTE in the NICAM configuration register) and the NICAM bit error count is higher than the value contained in this register, the signal of the first sound carrier (i.e. FM mono or AM sound) is selected for reproduction. The difference between upper and lower error limit constitutes a hysteresis to avoid frequent switching between NICAM and the program on the first sound carrier.
10.3.14.2 Definition
Table 35 Subaddress 17 (notes 1 and 2) MSB B7 Notes 1. The default setting at power-up is 01010000. 2. The lower bit error rate limit subaddress 16 x 1.74 x 10-5. 10.3.15 AUDIO MUTE CONTROL REGISTER B6 B5 B4 B3 B2 B1 LSB B0
10.3.15.1 Description
When any of these bits are set HIGH, the corresponding pair of output channels will be muted. A LOW bit allows normal signal output. There is a soft-mute facility for the Main and Auxiliary output channels to provide click-free muting independent of the volume control. This is switched on/off by bits MUTMAIN and MUTAUX.
10.3.15.2 Definition
Table 36 Subaddress 18 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 11111111. NAME MUTI2S2 MUTI2S1 MUTDAC MUTLINE MUTSC2 MUTSC1 MUTAUX MUTMAIN DESCRIPTION mute I2S2 outputs mute I2S1 outputs mute internal DAC mute line outputs mute SCART 2 outputs mute SCART 1 outputs mute Auxiliary outputs mute Main channels
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.16 DAC OUTPUT SELECT REGISTER
TDA9875
10.3.16.1 Description
This register is used to define both the signal source to be entered into the DAC and the mode of the digital matrix for signal selection. The DAC is used for signal output from digital sources at analog outputs. The two combinations of FM and NICAM apply to the (rare) condition that three different languages are being broadcast in an FM + NICAM system. They allow for a two-out-of-three selection for external use, such as recording.
10.3.16.2 Definition
Table 37 Subaddress 19 (note 1) MSB B7 DACGAIN2(2) Notes 1. The default setting at power-up is 00000000. 2. See Table 40. Table 38 Signal source left and right SIGNAL SOURCE B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 LEFT 0 1 0 1 0 1 0 1 FM left NICAM left I2S1 left I2S2 left ADC left AVL left FM mono FM mono RIGHT FM right NICAM right I2S1 right I2S2 right ADC right AVL right NICAM M1 NICAM M2 B6 B5 see Table 39 B4 B3 DACGAIN1(2) B2 B1 see Table 38 LSB B0
Table 39 Bits B6 to B4 (note 1) B6 0 0 0 0 1 Note 1. X = don't care. B5 0 0 1 1 X B4 0 1 0 1 X L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 40 Description of bits DACGAIN1 and DACGAIN2 NAME DACGAIN1, DACGAIN2 HIGH/LOW HIGH LOW 10.3.17 SCART 1 OUTPUT SELECT REGISTER FUNCTION
TDA9875
These bits can introduce some extra gain at the input to the DAC. DACGAIN1 adds 3 dB and DACGAIN2 adds 6 dB of gain, respectively. Sets a gain of 0 dB.
10.3.17.1 Description
This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode.
10.3.17.2 Definition
Table 41 Subaddress 20 (notes 1 and 2) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000001. 3. See Table 44. Table 42 Signal source B2 0 0 0 1 B1 0 1 1 0 B0 1 0 1 0 SIGNAL SOURCE SCART 2 input external input mono input DAC input B6 SC1GAIN(3) B5 B4 B3 X B2 B1 see Table 42 see Table 43 LSB B0
Table 43 Bits B5 and B4 B5 0 0 1 1 B4 0 1 0 1 L OUTPUT L input L input R input R input R OUTPUT R input L input R input L input
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 44 Description of bit SC1GAIN (note 1) NAME SC1GAIN HIGH/LOW HIGH FUNCTION
TDA9875
Activates the 3 dB gain stage at the SCART 1 output port. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 2 input to SCART 1 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. The audio signal will be output unchanged (0 dB gain).
LOW Note
1. A possibility to copy from SCART 1 input to SCART 1 output is not implemented. 10.3.18 SCART 2 OUTPUT SELECT REGISTER
10.3.18.1 Description
This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode.
10.3.18.2 Definition
Table 45 Subaddress 21 (notes 1 and 2) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 3. See Table 48. Table 46 Signal source B2 0 0 0 1 B1 0 1 1 0 B0 0 0 1 0 SIGNAL SOURCE SCART 1 input external input mono input DAC input B6 SC2GAIN(3) B5 B4 B3 X B2 B1 see Table 46 see Table 47 LSB B0
Table 47 Bits B5 and B4 B5 0 0 1 1 B4 0 1 0 1 L OUTPUT L input L input R input R input R OUTPUT R input L input R input L input
1998 Feb 13
48
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 48 Description of bit SC2GAIN (note 1) NAME SC2GAIN HIGH/LOW HIGH FUNCTION
TDA9875
Activates the 3 dB gain stage at the SCART 2 output port. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 1 input to SCART 2 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. The audio signal will be output unchanged (0 dB gain).
LOW Note
1. A possibility to copy from SCART 2 input to SCART 2 output is not implemented. 10.3.19 LINE OUTPUT SELECT REGISTER
10.3.19.1 Description
By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form. This register is used to characterize the signal to be output at the line output and define the output channel selector mode.
10.3.19.2 Definition
Table 49 Subaddress 22 (note 1) BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Note 1. The default setting at power-up is 00000000. Table 50 Bits B5 and B4 B5 0 0 1 1 B4 0 1 0 1 L OUTPUT L input L input R input R input R OUTPUT R input L input R input L input X X X LINSEL don't care don't care don't care select source for line output; see Table 51 NAME X LINGAIN DESCRIPTION don't care line output gain on/off; see Table 51 see Table 50
1998 Feb 13
49
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 51 Description of bits LINSEL and LINGAIN NAME LINSEL HIGH/LOW HIGH FUNCTION
TDA9875
Specifies that a signal from an analog source is being processed in the Main channel. Analog signal sources comprise SCART 1 input, SCART 2 input, external input and mono input, i.e. any input to the ADC. Specifies that a signal from a digital source is being processed in the Main channel. Digital signal sources comprise FM, NICAM, I2S1 input and I2S2 input. Activates the 3 dB gain stage at the line output port. The audio signal will be output unchanged (0 dB gain).
LOW LINGAIN HIGH LOW
10.3.20 ADC OUTPUT SELECT REGISTER
10.3.20.1 Description
This register is used to define the signal source for the ADC. There is no output channel selector, because all digital signal sinks of the ADC have their own matrix. Instead, a level adjustment facility for the ADC output is provided.
10.3.20.2 Definition
Table 52 Subaddress 23 (note 1) MSB B7 B6 see Table 53 Note 1. The default setting at power-up is 00000000. Table 53 Signal source B7 0 0 0 0 Table 54 Gain setting (notes 1 and 2) B4 0 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 B2 1 1 1 1 0 0 0 0 1 B1 1 1 0 0 1 1 0 0 1 B0 1 0 1 0 1 0 1 0 1 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 B6 0 0 1 1 B5 0 1 0 1 SIGNAL SOURCE SCART 1 input SCART 2 input external input mono input B5 B4 B3 B2 see Table 54 B1 LSB B0
1998 Feb 13
50
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
B4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes
B3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
B2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
B1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
GAIN SETTING (dB) +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1. An input of the DAC output to the ADC is meaningless and, therefore, not implemented. 2. A full-scale input signal to the ADC results in an output level of -6 dB (full-scale). This occurs prior to any gain setting. 10.3.21 MAIN CHANNEL SELECT REGISTER
10.3.21.1 Description
This register is used to define both the signal source to be processed in the Main (loudspeaker) channel and the mode of the digital matrix for signal selection.
10.3.21.2 Definition
Table 55 Subaddress 24 (notes 1 and 2) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 1998 Feb 13 51 B6 B5 see Table 57 B4 B3 X B2 B1 see Table 56 LSB B0
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 56 Signal source B2 0 0 0 0 1 Table 57 Bits B6 to B4 (note 1) B6 0 0 0 0 1 Note 1. X = don't care. 10.3.22 AUDIO EFFECTS REGISTER B5 0 0 1 1 X B4 0 1 0 1 X L OUTPUT L input L input R input R input L+R ------------2 B1 0 0 1 1 0 B0 0 1 0 1 0
TDA9875
SIGNAL SOURCE FM input NICAM input I2S1 input I2S2 input ADC input
R OUTPUT R input L input R input L input L+R ------------2
10.3.22.1 Definition
Table 58 Subaddress 25 (notes 1 and 2; see Table 62) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 3. See Table 61. 4. See Table 60. 5. See Table 59. Table 59 AVL control mode B1 0 0 1 1 B0 0 1 0 1 AVL MODE off/reset short decay medium decay long decay B6 X B5 SPATIAL1(3) B4 B3 B2 B1 AVL1(5) SPATIAL0(3) PSEUDO1(4) PSEUDO0(4) LSB B0 AVL0(5)
1998 Feb 13
52
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 60 Pseudo control setting B3 0 0 1 1 Table 61 Spatial control setting B5 0 0 1 1 Table 62 Description of Table 58 (notes 1, 2 and 3) NAME FUNCTION B4 0 1 0 1 B2 0 1 0 1
TDA9875
PSEUDO SETTING (Hz) off 300 200 150
SPATIAL SETTING (%) off 30 40 52
AVL0, AVL1 These bits set the mode of operation of the automatic volume level control function at the entrance to the Main (loudspeaker) channel. PSEUDO0, PSEUDO1 SPATIAL0, SPATIAL1 Notes 1. Switching the AVL off will reset the associated hardware to a defined state. 2. When the signal source for the Main channel is changed while the AVL is on, the AVL needs to be reset in order to avoid excessive settling times. This can be achieved by switching the AVL off and on again. 3. The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated in Table 60. There is a gain of 3 dB in the audio channel containing the filter. 10.3.23 VOLUME CONTROL REGISTERS (MAIN) These bits set the amount of the effect function (pseudo stereo) for mono signals in the Main channel. This function should be activated only in accordance with the result of the sound mode identification. These bits set the amount of the effect function (stereo base width expansion) for stereo signals in the Main channel. This function should be activated only in accordance with the result of the sound mode identification.
10.3.23.1 Description
These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies to the left channel signal, while the register at subaddress 27 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings.
1998 Feb 13
53
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.23.2 Definition
Table 63 Subaddresses 26 and 27 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B4 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA9875
VOLUME SETTING (dB) +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Feb 13
54
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
MSB B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 B3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VOLUME SETTING (dB) -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51
1998 Feb 13
55
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
MSB B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. The default setting at power-up is 10101100. B6 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 B3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 B2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOLUME SETTING (dB) -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -80 -81 -82 -83 mute (note 1)
1998 Feb 13
56
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.24 CONTOUR CONTROL REGISTER
TDA9875
10.3.24.1 Description
This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so, of decrease of the volume setting. The 0 dB contour setting is equal to contour off.
10.3.24.2 Definition
Table 64 Subaddress 28 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 10.3.25 BASS CONTROL REGISTER (MAIN) B6 X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X B4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CONTOUR GAIN (dB) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (note 2)
10.3.25.1 Description
This register is used to apply bass control to the left and right signal channels of the Main channel.
1998 Feb 13
57
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.25.2 Definition
Table 65 Subaddress 29 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA9875
BASS SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Feb 13
58
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.26 TREBLE CONTROL REGISTER (MAIN)
TDA9875
10.3.26.1 Description
This register is used to apply treble control to the left and right signal channels of the Main channel.
10.3.26.2 Definition
Table 66 Subaddress 30 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TREBLE SETTING (dB) +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Feb 13
59
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.27 AUXILIARY CHANNEL SELECT REGISTER
TDA9875
10.3.27.1 Description
This register is used to define both the signal source to be processed in the Auxiliary (headphone) channel and the mode of the digital matrix for signal selection.
10.3.27.2 Definition
Table 67 Subaddress 31 (notes 1 and 2) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. Table 68 Signal source B2 0 0 0 0 1 1 Table 69 Bits B6 to B4 (note 1) B6 0 0 0 0 1 Note 1. X = don't care. B5 0 0 1 1 X B4 0 1 0 1 X L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 B1 0 0 1 1 0 0 B0 0 1 0 1 0 1 SIGNAL SOURCE FM input NICAM input I2S1 input I2S2 input ADC input AVL input B6 B5 see Table 69 B4 B3 X B2 B1 see Table 68 LSB B0
1998 Feb 13
60
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY)
TDA9875
10.3.28.1 Description
These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32 applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings.
10.3.28.2 Definition
Table 70 Subaddresses 32 and 33 MSB B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B4 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOLUME SETTING (dB) +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7
1998 Feb 13
61
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
MSB B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOLUME SETTING (dB) -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48
1998 Feb 13
62
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
MSB B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. The default setting at power-up is 10101100. B6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOLUME SETTING (dB) -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -80 -81 -82 -83 mute (note 1)
1998 Feb 13
63
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.29 BASS CONTROL REGISTER (AUXILIARY)
TDA9875
10.3.29.1 Description
This register is used to apply bass control to the left and right signal channels of the Auxiliary channel.
10.3.29.2 Definition
Table 71 Subaddress 34 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 BASS SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Feb 13
64
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.30 TREBLE CONTROL REGISTER (AUXILIARY)
TDA9875
10.3.30.1 Description
This register is used to apply treble control to the left and right signal channels of the Auxiliary channel.
10.3.30.2 Definition
Table 72 Subaddress 35 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TREBLE SETTING (dB) +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
1998 Feb 13
65
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER
TDA9875
10.3.31.1 Definition
Table 73 Subaddress 36 (notes 1 and 2) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 3. System clock frequency select; see Table 74. 4. System clock output on/off; see Table 75. 5. Serial output format; see Table 75. 6. I2S-bus outputs on/off; see Table 75. Table 74 System clock frequency select B4 0 0 1 1 Table 75 Description of Table 73 NAME I2SOUT HIGH/LOW HIGH LOW I2SFORM HIGH LOW SYSOUT HIGH LOW FUNCTION Enables the output of serial audio data (2 pins) plus serial bit clock and word select in a format determined by the I2SFORM bit. The TDA9875 is then an I2S-bus master. the outputs mentioned will be 3-stated, thereby improving the EMC performance an MSB-aligned, MSB-first output format is selected, i.e. a level change at the word select pin indicates the beginning of a new audio sample the standard I2S-bus output format is selected enables the output of a system (or master) clock signal at pin SYSCLK the output will be off, thereby improving the EMC performance B3 0 1 0 1 SYSCLK OUTPUT 256fs 384fs 512fs 768fs FREQUENCY (MHz) 8.192 12.288 16.384 24.576 B6 X B5 X B4 SYSCL1(3) B3 SYSCL0(3) B2 SYSOUT(4) B1 I2SFORM(5) LSB B0 I2SOUT(6)
1998 Feb 13
66
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.32 I2S1 OUTPUT SELECT REGISTER
TDA9875
10.3.32.1 Description
This register is used to define both the signal source to be output at I2S1 and the mode of the digital matrix for signal selection.
10.3.32.2 Definition
Table 76 Subaddress 37 (notes 1 and 2) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. Table 77 Signal source (note 1) B2 0 0 0 0 1 1 1 1 Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. Table 78 Bits B6 to B4 (note 1) B6 0 0 0 0 1 Note 1. X = don't care. B5 0 0 1 1 X B4 0 1 0 1 X L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 SIGNAL SOURCE FM output NICAM output I2S1 input I2S2 input ADC output AVL output Auxiliary output Main output B6 B5 see Table 78 B4 B3 X B2 B1 see Table 77 LSB B0
1998 Feb 13
67
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.33 I2S1 INPUT LEVEL ADJUST REGISTER
TDA9875
10.3.33.1 Description
This register is used to adjust the input level at the I2S1 interface. Left and right signal channel are treated identically.
10.3.33.2 Definition
Table 79 Subaddress 38 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1998 Feb 13
68
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.34 I2S1 OUTPUT LEVEL ADJUST REGISTER
TDA9875
10.3.34.1 Description
This register is used to adjust the output level at the I2S1 interface. Left and right signal channel are treated identically.
10.3.34.2 Definition
Table 80 Subaddress 39 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1998 Feb 13
69
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.35 I2S2 OUTPUT SELECT REGISTER
TDA9875
10.3.35.1 Description
This register is used to define both the signal source to be output at I2S2 and the mode of the digital matrix for signal selection.
10.3.35.2 Definition
Table 81 Subaddress 40 (notes 1 and 2) MSB B7 X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. Table 82 Signal source (note 1) B2 0 0 0 0 1 1 1 1 Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. Table 83 Bits B6 to B4 (note 1) B6 0 0 0 0 1 Note 1. X = don't care. B5 0 0 1 1 X B4 0 1 0 1 X L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 SIGNAL SOURCE FM output NICAM output I2S1 input I2S2 input ADC output AVL output Auxiliary output Main output B6 B5 see Table 83 B4 B3 X B2 B1 see Table 82 LSB B0
1998 Feb 13
70
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.36 I2S2 INPUT LEVEL ADJUST REGISTER
TDA9875
10.3.36.1 Description
This register is used to adjust the input level at the I2S2 interface. Left and right signal channel are treated identically.
10.3.36.2 Definition
Table 84 Subaddress 41 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1998 Feb 13
71
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.37 I2S2 OUTPUT LEVEL ADJUST REGISTER
TDA9875
10.3.37.1 Description
This register is used to adjust the output level at the I2S2 interface. Left and right signal channel are treated identically.
10.3.37.2 Definition
Table 85 Subaddress 42 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 mute
1998 Feb 13
72
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.38 BEEPER FREQUENCY CONTROL REGISTER
TDA9875
10.3.38.1 Description
This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main and Auxiliary channel output DAC. Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than the 390 Hz beep.
10.3.38.2 Definition
Table 86 Subaddress 43 (notes 1 and 2) MSB B7 X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00000000. 10.3.39 BEEPER VOLUME CONTROL REGISTER B6 X X X X X X X X B5 X X X X X X X X B4 X X X X X X X X B3 X X X X X X X X B2 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 LSB B0 1 0 1 0 1 0 1 0 GENERATED FREQUENCY (Hz) 25000 7040 3580 1770 1270 900 640 390
10.3.39.1 Description
This register is used to set the beeper volume. The gain setting is relative to digital full-scale at the input to the Main and Auxiliary channel output DACs. The beeper volume is independent of any other volume setting. The beeper signal is added to the Main and Auxiliary channel output signals in the 2 x fs domain. The beeper volume should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to avoid output signal distortion due to overload.
1998 Feb 13
73
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.39.2 Definition
Table 87 Subaddress 44 (note 1) MSB B7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes 1. X = don't care. 2. The default setting at power-up is 00100000. B6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA9875
GAIN SETTING (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 -51 -54 -57 -60 -63 -66 -69 -72 -75 -78 -81 -84 -87 -90 -93 mute (note 2)
1998 Feb 13
74
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.3.40 BASS BOOST CONTROL REGISTER
TDA9875
10.3.40.1 Description
This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function must be used with care in order to avoid clipping distortion at high volume settings. More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then has full control over this 2nd-order filter and can, within limits, realize bass equalizers with arbitrary centre frequencies, Q factors and boost/cut settings.
10.3.40.2 Definition
Table 88 Subaddress 45 (note 1; see Table 89) MSB B7 Note 1. The default setting at power-up is 00000000. Table 89 Gain setting B7, B3 1 1 1 0 0 0 0 0 0 0 0 B6, B2 0 0 0 1 1 1 1 0 0 0 0 B5, B1 1 0 0 1 1 0 0 1 1 0 0 B4, B0 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) 20 18 16 14 12 10 8 6 4 2 0 CORNER FREQUENCY (Hz) 350 350 350 350 350 350 350 350 350 350 350 B6 B5 B4 B3 B2 B1 LSB B0
1998 Feb 13
75
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.4 Slave transmitter mode
TDA9875
As a slave transmitter, the TDA9875 provides 13 registers with status information and data, a part of which is for Philips internal purposes only. These registers can be accessed by means of subaddresses. Table 90 General format for reading data from the TDA9875 S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA NAm P
Table 91 Explanation of Tables 90 and 92 BIT S SLAVE ADDRESS 0 ACK SUBADDRESS Sr 1 DATA NAm Am P START condition 7-bit device address data direction bit (write to device) acknowledge (by the slave) address of register to read from repeated START condition data direction bit (read from device) data byte read from register not acknowledge (by the master) acknowledge (by the master) STOP condition FUNCTION
Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the TDA9875. In this situation, the subaddress is automatically incremented after each data byte, which results in reading the sequence of data bytes from successive register locations, starting at SUBADDRESS. Table 92 Format of a transmission using automatic incrementing of subaddresses S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA BYTE Am(1) DATA NAm P
Note 1. n data bytes with auto-increment of subaddresses. Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master). The subaddresses `wrap around' from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in hexadecimal notation.
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
Table 93 Overview of the slave transmitter registers (note 1) SUBADDRESS (DECIMAL) MSB 0 1 2 3 4 5 6 7 251 252 253 254 255 Note s s e d c l l X a a a d s s s e d c l l X a a a d s s s e d X l l X a a a d s DATA FUNCTION LSB s s e d c l l c a a a d s s s e d c l l c a a a d s s s e d d l l c a a a d s s s e d d l l c a a a d s s s e d d l l c a a a d s
TDA9875
device status (power-on, identification, etc.) NICAM status NICAM error count additional data (LSB) additional data (MSB) level read-out (MSB) level read-out (LSB) SIF level test register 3 test register 2 test register 1 device identification code software identification code
1. X indicates a bit that has not yet been assigned to a function. Its meaning is `don't care', its return value is a zero. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of registers for the identification of individual members and some key parameters in a family of devices. A detailed description of the slave transmitter registers is given in below: 10.4.1 DEVICE STATUS REGISTER
10.4.1.1
Definition
Table 94 Subaddress 0 BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) NAME P2IN P1IN RSSF AMSTAT VDSP IDDUA IDSTE X DESCRIPTION input from port 2 input from port 1 reserve sound switching flag auto-mute status identification of NICAM sound identification of FM dual sound identification of FM stereo don't care
1998 Feb 13
77
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.4.1.2 Description
TDA9875
Table 95 Description of Table 94 NAME IDSTE IDDUA VDSP AMSTAT HIGH/LOW HIGH LOW - HIGH LOW - This bit is HIGH if an FM dual-language signal has been identified. When neither IDSTE nor IDDUA are set, the received signal is assumed to be FM mono. indicates that digital transmission is a sound source (NICAM) the transmission is either data or currently undefined format (NICAM) if this bit is HIGH, it indicates that the auto-muting function has switched from NICAM to the program of the first sound carrier (i.e. FM mono or AM in NICAM L systems) This bit is a copy of the C4 bit in the NICAM status register. It indicates that the FM (or AM for standard L) sound matches the digital transmission and auto-muting should be enabled. auto-muting should be disabled, as analog and digital sound are different these bits reflect the status of the corresponding general purpose port pins, see Section 10.3.2 FUNCTION this bit is HIGH if an FM stereo signal has been identified
RSSF
HIGH
LOW P1IN, P2IN -
10.4.2
NICAM STATUS REGISTER
10.4.2.1
Definition
Table 96 Subaddress 1 BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) NAME C4 C3 C2 C1 OSB CFC S/MB D/SB synchronization bit configuration change identification of NICAM stereo identification of NICAM dual mono DESCRIPTION NICAM application control bits
1998 Feb 13
78
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.4.2.2 Description
TDA9875
Table 97 Description of Table 96 NAME D/SB S/MB CFC OSB C1, C2, C3, C4 HIGH/LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW if this bit is HIGH, it indicates a configuration change at the 16 frame (C0) boundary indicates that the device has both frame and C0 (16 frame) synchronization the audio output from the NICAM part should be digital silence these bits correspond to the control bits C1 to C4 in the NICAM transmission if this bit is HIGH it indicates stereo mode FUNCTION if this bit is HIGH it indicates dual mono mode
10.4.2.3
Notes
The TDA9875 does not support the Extended Control Modes. Therefore, the program of the first sound carrier (i.e. FM mono or AM) is selected for reproduction in case bit C3 is set HIGH, independent of bit AMUTE in the NICAM configuration register being set or not. When a NICAM transmitter is switched off, the device will lose synchronization. In this situation the program of the first sound carrier is selected for reproduction, independent of bit AMUTE being set or not. 10.4.3 NICAM ERROR COUNT REGISTER
10.4.3.1
Description
Bits B7 to B0 contain the number of errors occurring in the previous 128 ms period. The register is updated every 128 ms.
10.4.3.2
Definition
Table 98 Subaddress 2 MSB B7 B6 B5 B4 B3 B2 B1 LSB B0
1998 Feb 13
79
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.4.4 ADDITIONAL DATA REGISTERS
TDA9875
10.4.4.1
Description
These two bytes provide information on the additional data bits. ADBYTE0 is stored at subaddress 3.
10.4.4.2
Definition
Table 99 Subaddress 3 BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Table 100 Subaddress 4 BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Table 101 Description of Tables 99 and 100 NAME AD10 to AD0 CI1, CI2 SAD OVW HIGH/LOW - - HIGH LOW - comprise the additional data word these are CI bits decoded by majority logic from the parity checks of the last ten samples in a frame new additional data is written into the IC reset, when the additional data bits are read if this bit is HIGH, new additional data bits are written to the IC without the previous bits being read FUNCTION NAME OVW SAD X (don't care) CI1 CI2 AD10 AD9 AD8 NAME AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1998 Feb 13
80
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.4.5 LEVEL READ-OUT REGISTERS
TDA9875
When the SIF AGC is off, this register returns the contents of the AGC gain register.
10.4.5.1
Description
These two bytes constitute a word that provides data from a location that has been specified with the monitor select register. The most significant byte of the data is stored at subaddress 5. If peak-level monitoring has been selected, the peak-level monitoring register is cleared and monitoring resumes after its contents has been transferred to these two bytes.
10.4.6.2
Definition
Table 104 Subaddress 7 (note 1) MSB B7 Note 1. Bits B5, B6 and B7 are don't care. B6 B5 B4 B3 B2 B1 LSB B0
10.4.5.2
Definition
10.4.7 BIT 7 (most significant bit or sign bit) 6 5 4 3 2 1 0 TEST REGISTER 3
Table 102 Subaddress 5
10.4.7.1
Description
This register contains, as a binary number, the highest memory address used for the Coefficient RAM (CRAM, expert mode). The first version will have the identification 01111111.
10.4.7.2
Definition
Table 105 Subaddress 251 MSB B7 B6 B5 B4 B3 B2 B1 LSB B0
Table 103 Subaddress 6 10.4.8 BIT 7 6 5 4 3 2 1 0 (least significant bit) 10.4.6 SIF LEVEL REGISTER Table 106 Subaddress 252 MSB B7 B6 B5 B4 B3 B2 B1 LSB B0 TEST REGISTER 2
10.4.8.1
Description
This register contains, as a binary number, the highest subaddress used for slave receiver registers. The first version will have the identification 00101101.
10.4.8.2
Definition
10.4.6.1
Description
10.4.9
TEST REGISTER 1
When the SIF AGC is on, bits B4 to B0 of this register contain a number that gives an indication of the SIF input level. That number can be interpreted in the same way as the AGC gain register setting (see Section 10.3, subaddress 0), i.e., if the SIF AGC were set to a fixed gain and the same number loaded into the AGC gain register, the current SIF input signal level would generate an SIF ADC output close to full-scale.
10.4.9.1
Description
This register contains, as a binary number, the highest subaddress used for slave transmitter (status) registers. The first version will have the identification 00000111.
1998 Feb 13
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
10.4.9.2 Definition 10.4.11.2 Definition
Table 109 Subaddress 255 LSB B6 B5 B4 B3 B2 B1 B0 MSB B7 10.5 B6 B5 B4 B3
TDA9875
Table 107 Subaddress 253 MSB B7
LSB B2 B1 B0
10.4.10 DEVICE IDENTIFICATION CODE
Expert mode
10.4.10.1 Description
There will be several devices in the digital TV sound processor family, with TDA9875 being the first member. This byte is used to identify the individual family members purely for Philips internal use. The first version will have the identification 00000000.
In addition to the slave receiver and slave transmitter modes previously described, there is a special `expert' mode that gives direct write access to the internal CRAM of the DSP. In this mode, transferred data contain 12-bit-wide coefficients. As those coefficients bypass on-chip coefficient look-up tables for many functions, they directly influence the processing of signals within the DSP. This mode must be used with great care. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses.
10.4.10.2 Definition
Table 108 Subaddress 254 MSB B7 B6 B5 B4 B3 B2 B1 LSB B0
10.4.11 SOFTWARE IDENTIFICATION CODE
10.4.11.1 Description
It is likely that during the life time of this family of devices several versions of the DSP software will be made, e.g., to accommodate new application concepts, respond to customer wishes, etc. This byte is used to identify the different releases purely for Philips internal use. The first version will have the identification 00000000. Table 110 General format for entering the expert mode and writing coefficients into the TDA9875 S SLAVE ADDRESS 0 ACK 10000000 ACK CRAM ADDRESS ACK DATA ACK DATA ACK P
Table 111 Explanation of Table 110 BIT S SLAVE ADDRESS 0 ACK 10000000 CRAM ADDRESS DATA P START condition 7-bit device address data direction bit (write to device) acknowledge pattern to enter the expert mode start address of coefficient RAM to write to data byte containing part of a coefficient STOP condition FUNCTION
1998 Feb 13
82
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
As the coefficients do not fit into one data byte, they have to be split and arranged (see Table 112). The most significant bit is transferred first. Table 112 General format (notes 1, 2 and 3) BYTE 1. data byte 2. data byte Notes 1. X = don't care. 2. MST = most significant third. 3. LST = least significant third. The general format described in Table 112 shows the minimum number of data bytes required, i.e. two bytes for the transfer of a single coefficient. Should more than one coefficient be sent, then the CRAM address will be automatically incremented after each coefficient, resulting in writing the sequence of coefficients into successive memory locations, starting at CRAM ADDRESS. A transmission can start with any valid CRAM address. If two coefficients are to be transferred, they are arranged as shown in Table 113. Table 113 Transfer of two coefficients BYTE 1 data byte 2 data byte 3 data byte a a b a a b a a b DATA a a b a b b a b b a b b a b b DESCRIPTION 2 MST of 1st coefficient 1 LST of 1st coefficient + 1 MST of 2nd coefficient 2 LST of 2nd coefficient a a a a a a DATA a a a X a X a X a X DESCRIPTION 2 MST of 1st coefficient 1 LST of 1st coefficient
With any odd number of coefficients to be transferred, the least significant nibble of the last byte is regarded as containing don't care data. As the transfer of coefficients cannot be accomplished within one audio sample period, it is necessary that received coefficients be buffered and made active all at the same time to avoid audio signal transients. The receive buffer is designed to store up to 8 coefficients in addition to the CRAM address. Each byte that fits into the buffer is acknowledged with ACK (acknowledge). If an attempt is made to write more coefficients than the buffer can store, the device acknowledges with NACK (not acknowledge) and any further coefficients are ignored. Coefficients that are already in the receive buffer remain intact. An expert mode transfers ends when the I2C-bus STOP condition or a repeated START condition has been detected. Only those coefficients that have been received during the last transmission will then be copied from the buffer to the CRAM.
To make efficient and correct use of the expert mode, it is recommended to transfer all coefficients for any one function in a single transmission. There is no checking of memory addresses and the automatic incrementing of addresses does not stop at the highest used CRAM address. The user of this expert mode must be fully acquainted with the relevant procedures. More information concerning the functions of this device, such as filter structures, the number of coefficients per function, their default values, memory addresses, etc., can be supplied on request at a later date. 11 I2S-BUS DESCRIPTION The feature interface of the TDA9875 contains two serial audio inputs and outputs and associated clock signals. It can be used to supply, for example, audio signals from received TV programs to a digital audio output device (AES/EBU format), or import serial audio signals from other sources for reproduction through the TV set's 83
1998 Feb 13
Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
loudspeaker and/or headphone channels. Apart from such simple data input or output, it is also possible to run audio signals through an external DSP, which performs some additional functions, such as room simulation, Dolby Surround Pro Logic etc. and feed those signals back into the loudspeaker and/or headphone channels of the TDA9875. Two serial audio formats are supported at the feature interface, i.e. the I2S-bus format and a very similar MSB-aligned format. The difference is illustrated in Fig.7. In both formats the left audio channel of a stereo sample pair is output first and is placed on the serial data line (SDI for input, SDO for output) when the word select line (WS) is LOW. Data is written at the trailing edge of SCK and read at the leading edge of SCK. The most significant bit is sent first. At power-up, the outputs of the feature interface are 3-stated to reduce EMC and allow for combinations with other ICs. If output is desired, it has to be activated by means of an I2C-bus command. When the output is enabled, the serial audio data can be taken from pins SDO1 and SDO2. Depending on the signal source, switch and matrix positions, the output can be either mono, stereo or dual language sound on either output. The word select output is clocked with the audio sample frequency at 32 kHz. The serial clock output (SCK) is clocked at a frequency of 2.048 MHz. This means, that there are 64 clock pulses per pair of stereo output samples, or 32 clock pulses per sample. Depending again on the signal source, the number of significant bits on the serial data outputs, SDO1 and SDO2, is between 14 and 18.
TDA9875
Apart from just feeding a digital audio device, such as a DAC or an AES/EBU transmitter, the serial data outputs can be connected directly to the serial inputs (loop-back connection) or first to an external device, e.g. a feature DSP such as the SAA7710 and then back to the serial inputs. In all of these configurations, the SCK and WS clocks will be generated by the TDA9875, which then is the I2S-bus master. The serial data inputs, SDI1 and SDI2, are active at all times, independent of the serial data outputs being on or off. When the serial data outputs are off (either after power-up or via the appropriate I2C-bus command) serial data and clocks WS and SCK from a separate digital audio source can be fed into the TDA9875, be processed and output in accordance with internal selector positions, provided that the following criteria are met: * 32 kHz audio sample frequency * 32 clock bits per sample * External timing and data synchronized to TDA9875. In such cases, the external source is the I2S-bus master and the TDA9875 is the I2S-bus slave. To support synchronization of external devices or as a master clock for them, a symmetrical system clock output, SYSCLK, is available from the TDA9875. At power-up it is off. It can be enabled and the output frequency set via an I2C-bus command. Available output frequencies are 8.192, 12.288, 16.384 and 24.576 MHz.
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Preliminary specification
Digital TV Sound Processor (DTVSP)
TDA9875
handbook, full pagewidth
SCK
WS
SD
LSB
MSB
LSB
MSB
MGK112
one sample
a. I2S-bus format.
handbook, full pagewidth
SCK
WS
SD
LSB
MSB
LSB
MSB
MGK113
one sample
b. MSB-aligned format.
Fig.7 Serial audio interface formats.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
12 EXTERNAL COMPONENTS
TDA9875
handbook, full pagewidth
PCLK NICAM data ADDR1 SCL SDA
PCLK NICAM ADDR1 SCL SDA VSSA1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDD2 LOR LOL MOL C18 MOR VDDA3 AUXOL C23 AUXOR C25 VSSA3 PCAPL PCAPR Vref3 SCOL2 SCOR2 VSSA4 VSSD2 SCOL1 SCOR1 Vref2 CAPR1 CAPR2 VSSA2 CAPL2 CAPL1 Vref(n) Vref(p) C36 47 F R9 270 C38 C35 220 pF R8 270 C34 220 pF C32 2.2 F C31 2.2 F C33 47 F C28 47 F C30 2.2 F C20 C21 C15 C14
R7 47 F 1.5
+5 V LINER
2.2 F
C16 LINEL C17 MAINL C19 2.2 F MAINR R6 10 C24 2.2 F AUXR +5 V AUXL
2.2 F 10 nF
10 nF 2.2 F 47 F C22
+5 V
R1 10 C1 4.7 F
VDDA1 R2 Iref 10 k P1 C2 SIF2 Vref1 SIF1 ADDR2 VSSD1
10 nF 2.2 F 10 nF
P1 SIFSAT C3 47 pF
C26 10 nF C27 10 nF C29 SC2OL 2.2 F SC2OR
100 nF C4 SIFTV 47 pF ADDR2
+5 V
R3 1.5 D1 C5 47 F C7 33 pF 24.576 MHz C6 1 F
VDDD1 CRESET XTALO
TDA9875
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MGK114
L1 3.3 H
R4 39 k
BB135
C8 33 pF XTALI Vtune P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1
SC1OL SC1OR
R5 10 k P2 C10 33 nF C9 330 nF R15 20 k WS SDO2 SDO1 SDI2 SDI1 SYSCLK SCK
R10 C37 10 47 F
+5 V
VDDA2 SCIL2 R11 15 k SCIR2 VSSG SCIL1 SCIR1 R14
SC2IL R12 330 nF C39 SC2IR 15 k 330 nF C40 SC1IL 15 k 330 nF C41 SC1IR 330 nF
C11 MONOIN 470 nF C12 EXTR
MONOIN TEST2 EXTIR EXTIL
R13
470 nF C13 EXTL 470 nF
15 k
Fig.8 Schematic for measurements.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
13 PACKAGE OUTLINE SDIP64: plastic shrink dual in-line package; 64 leads (750 mil)
TDA9875
SOT274-1
seating plane
D
ME
A2 A
L
A1 c Z e b1 b 64 33 wM (e 1) MH
pin 1 index E
1
32
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.84 A1 min. 0.51 A2 max. 4.57 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 58.67 57.70 E (1) 17.2 16.9 e 1.778 e1 19.05 L 3.2 2.8 ME 19.61 19.05 MH 20.96 19.71 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT274-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-10-13 95-02-04
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Preliminary specification
Digital TV Sound Processor (DTVSP)
14 SOLDERING 14.1 Introduction
TDA9875
with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.3 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 14.2 Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact 15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
NOTES
TDA9875
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
NOTES
TDA9875
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Philips Semiconductors
Preliminary specification
Digital TV Sound Processor (DTVSP)
NOTES
TDA9875
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
Internet: http://www.semiconductors.philips.com
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/1200/02/pp92
Date of release: 1998 Feb 13
Document order number:
9397 750 03003

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